With smaller geometry of fabrication process, the number and type of defects on a chip increase exponentially. Considering the number of different faults on a given chip, more number of patterns is needed to target these smaller geometry faults. This leads to the need for efficient pattern generation techniques on any nanometer chip. But obtaining satisfactory coverage for transition delay test, with limited test pattern count, is a challenge. For example, with limited memory on the tester, the number of test patterns cannot be increased to achieve higher test coverage.
Inefficient test grouping/clock sequencing may result in inefficient pattern allocation and higher test coverage in some of the At-Speed Test groups, while providing poor coverage numbers for other test groups, long pattern generation time (ATPG) and wrong test failures on real hardware due to incorrect domain crossings. Inefficient test grouping/clock sequencing may further result in increased power droop in one group versus other groups, depending on the number of active faults, as well as a reduction in coverage on domain crossings.
Also, currently At-Speed test-groups and clock sequencing are created by hand with no well defined process. For example, clock designers will manually create test-groups/clock sequence per certain guidelines. This manual process is tedious, time consuming and error prone. Also, asynchronous domains fail on the tester if they communicate. And, in a test group, there are additional constraints driving the separation of certain clocking elements that could increase power drooping if tested together, which may be overlooked in manual processes. For example, grouping multiple PLLs in a same test group may cause characterization issues if they cannot be handled by the same reference clock.